The term FinFET typically refers to a nonplanar, double-gate transistor. Integrated circuits that include FinFETs may be fabricated on a bulk silicon substrate or, more commonly, on a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a semiconductor substrate, and a buried insulator layer, e.g., a buried oxide layer that separates and electrically isolates the semiconductor substrate from the SOI layer. Each FinFET generally includes a narrow vertical fin body of single crystal semiconductor material with vertically-projecting sidewalls. A gate contact or electrode intersects a channel region of the fin body and is isolated electrically from the fin body by a thin gate dielectric layer. At opposite ends of the fin body are heavily-doped source/drain regions.
As technology node sizes shrink, it may be beneficial to utilize strained FinFETs. A strained FinFET includes a strained fin body that includes distorted crystal lattices, relative to silicon, which generally improves electron and hole mobility though the strained fin body. The strained fin bodies of strained FinFETs may be fabricated from a strained layer epitaxially grown upon on an SRB layer. Such a technique may be particularly beneficial since epitaxy defects may be confined to the SRB layer, leaving the strained layer substantially defect free. However, challenges exists in the formation and integration of source drain regions in these strained FinFETs.
Particularly, if the source drain regions contact the SRB layer having epitaxy defects, excessive source drain junction leakage may occur. Further, source drain punch through may also occur due to excessive dopant diffusion through the defective SRB layer underneath the channel region. Even further, portions of the strained fin bodies may remained undoped resulting in higher resistance.